A flexible computing platform for artificial intelligence tasks, Scientists have developed a programmable field-programmable gate arrays (FPGA) computing device that can be adjusted by the user for maximum performance in AI applications.

Compared to the hardware currently used, the system increases circuit density by a factor of 12. It is also expected that energy consumption will be reduced by 80%.

This evolution can lead to flexible artificial intelligence (AI) solutions that offer increased performance while using far less power.

AI becomes part of the daily routine of almost all users. Smartphone apps with carpooling like Uber, Gmail spam filters, and smart home devices like Siri and Nest rely on AI.

However, implementing this algorithm often requires a large amount of computing power, which means high electricity costs and large CO2 emissions. A flexible computing platform for artificial intelligence tasks.

A system that can please the human brain to optimize computer circuits for each task will significantly improve energy efficiency.

We usually think of hardware that contains physical logic gates and transistors on a computer processor, as determined by the manufacturer.

However, portable programmable arrays are special logic elements that can be directed to custom logic applications by users “on the spot”.

The research team used non-volatile “switches” that remained connected until the user decided to reconfigure them. With the new nano manufacturing process, they can package twelve times as many items in settings such as a grating as a cross belt. A flexible computing platform for artificial intelligence tasks.

By reducing the distance, electronic signals must be directed, the device ultimately requires 80% less electricity.

Our system, based on a programmable arrangement of fields, has a very fast design cycle. Researchers say: It can be reprogrammed every day if you want to get the highest processing power for each new AI application.

Use via the switch also eliminates the need to program the silicon area needed on previous FPGA devices.